Manuel d'utilisation / d'entretien du produit C6713CPU du fabricant Kane Industries
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H ARDWARE R EFERENCE G UIDE Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 1 Orsys Orth System GmbH, Am Stadtgraben 25, 88677 Markdorf , Germany http://www.
H ARDWARE R EFERENCE G UIDE MICRO - LINE C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 2 Contents 1 PREFACE ..........................................................................................................
H ARDWARE R EFERENCE G UIDE MICRO - LINE C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 3 3.3 Internal fast SRAM ......................................................................................................
H ARDWARE R EFERENCE G UIDE MICRO - LINE C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 4 7.2.3 Configuring for HPI or McASP1 Usage ............................................................................... 47 7.
H ARDWARE R EFERENCE G UIDE MICRO - LINE C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 5 List of Tables Table 1: Memory map of the processor .........................................................................
H ARDWARE R EFERENCE G UIDE MICRO - LINE C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 6 1 Preface This document describes the hardware of the C6713CPU board. It is intended to get an overview of the board and its features.
H ARDWARE R EFERENCE G UIDE MICRO - LINE C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 7 Configuration parameters, function names, path names and file names are written in italic typeface. Example: dev_id Source code examples are given in a small, fixed-width typeface.
H ARDWARE R EFERENCE G UIDE MICRO - LINE C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 8 1.5 Revision History Revision Changes 0.1 ORSYS internal preliminary version / April 2005 0.5 First public preliminary version / May 2005 0.
H ARDWARE R EFERENCE G UIDE MICRO - LINE C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 9 2 Hardware Overview The micro-line ® C6713CPU is a high performance DSP b.
H ARDWARE R EFERENCE G UIDE MICRO - LINE C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 10 2.1 Block Diagram of the C6713CPU Figure 1: Block diagram of the C6713 CP.
H ARDWARE R EFERENCE G UIDE MICRO - LINE C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 11 C9 green LED ( PLD) red LED (PLD) yellow LE D (FPGA ) JT AG conne c tor D.
H ARDWARE R EFERENCE G UIDE MICRO - LINE C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 12 2.2 Connectors 2.2.1 micro-line ® Connectors The micro-line ® connectors are the main I/O connectors of the C6713CPU. They provide access to all signals that are needed for a wide range of I/O connectivity.
H ARDWARE R EFERENCE G UIDE MICRO - LINE C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 13 interfacing over for the majority of the micro-line ® connector pins. The user is no longer restricted to a fixed I/O logic.
H ARDWARE R EFERENCE G UIDE MICRO - LINE C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 14 can be software reconfigured by PLL settings. It can also be generated by the FPGA, allowing any clock frequency up to 100 MHz.
H ARDWARE R EFERENCE G UIDE MICRO - LINE C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 15 DSP-internal temperature is roughly 15 degrees Celsius above the temperature measured by the sensor. Software drivers for the temperature sensor are included in the development kits, see [20] for details.
H ARDWARE R EFERENCE G UIDE MICRO - LINE C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 16 2.4.1 User Prog rammable LED's (PLD) These LED's are controlled by PLD registers (see chapter 3. 10). They can be switched on and off by application software to display certain events or states.
H ARDWARE R EFERENCE G UIDE MICRO - LINE C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 17 CE0 is used for on-board SDRAM CE1 is used for on-board flash memory , PLD and FPGA registers.
H ARDWARE R EFERENCE G UIDE MICRO - LINE C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 18 2.5.6 Timers The TMS320C6713 DSP provides two independent 32-bit general purpose timers. The timers support two signaling modes and can be clo cked by an internal or an external source.
H ARDWARE R EFERENCE G UIDE MICRO - LINE C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 19 2.5.9 DMA The TMS320C6713 DSP provides an enhanced DMA (EDMA) controller with 16 channels and 16 possible synchronization events.
H ARDWARE R EFERENCE G UIDE MICRO - LINE C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 20 3 Memory Maps and Description of the PLD Registers 3.1 TMS320C6713 M emory Map The memory map of the TMS320C6713 is divided into several sections: internal memory DSP peripherals EMIF CE spaces CE0 .
H ARDWARE R EFERENCE G UIDE MICRO - LINE C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 21 3.2 C6713CPU Address Map The table below shows how the C6713CPU uses the .
H ARDWARE R EFERENCE G UIDE MICRO - LINE C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 22 3.7 Endianness When data is transferred between the C6713CPU board and external hardware over the micro- line ® connector it is important to know how data is stored in memory.
H ARDWARE R EFERENCE G UIDE MICRO - LINE C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 23 3.8 EMIF Configuration All accesses to off-DSP-chip peripherals, such as on-board SDRAM, the UART or the FPGA are performed by the DSP's external memory inte rface (EMIF).
H ARDWARE R EFERENCE G UIDE MICRO - LINE C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 24 base address 2 register name register mnemonic 9010 0000h Hardware config.
H ARDWARE R EFERENCE G UIDE MICRO - LINE C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 25 CPUSPEED: This bit can be used by application software to determine the DSP speed version and to program the DSP's PLL accordingly.
H ARDWARE R EFERENCE G UIDE MICRO - LINE C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 26 7 6 5 4 3 0 RED_LED GREEN_LED RESERVED r, w, 00 r, w, 11 RED_LED: RED_LED.
H ARDWARE R EFERENCE G UIDE MICRO - LINE C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 27 7 6 5 4 3 0 SDA_STAT SDA_CTL SCL_S TAT SCL_CTL RESERVED r, 1 r, w, 1 r, 1 r, w, 1 SDA_STAT: retrieves the current state of the SDA line.
H ARDWARE R EFERENCE G UIDE MICRO - LINE C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 28 WDG_RST: The WD_RST pin of the PLD is connected to the watch dog input of the reset generator. If the watchdog is enabled the WD_RST pin must be set to 1 at least once per second.
H ARDWARE R EFERENCE G UIDE MICRO - LINE C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 29 4 Boot Process and Default Setup of the C6713CPU After reset or power up the C6713CPU boots the Flash File System from flash memory.
H ARDWARE R EFERENCE G UIDE MICRO - LINE C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 30 5 Using the Flash File System The Flash File System of the C6713CPU consi.
H ARDWARE R EFERENCE G UIDE MICRO - LINE C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 31 6 Description of the micro-line ® Board Connectors 6.1 Location of the Connectors For the micro-line ® connectors, Pin 1 is marked by a black sq uare in Figure 6.
H ARDWARE R EFERENCE G UIDE MICRO - LINE C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 32 6.2 Connector Overview Table 10 gives an overview about usage of the micro-line ® connectors, including the ' classic' usage as peripheral interface as used with previous CPU boards.
H ARDWARE R EFERENCE G UIDE MICRO - LINE C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 33 shared with Default signal name Interface signal micro-line ® connector .
H ARDWARE R EFERENCE G UIDE MICRO - LINE C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 34 shared with Signal interface signal micro-line ® connector AXR0[7] FSR1 .
H ARDWARE R EFERENCE G UIDE MICRO - LINE C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 35 6.4 Pinout of the JTAG Connector Pin Signal pin signal used for A1 FPGA_TMS B1 GND A2 FPGA_TDI B2 GND A3 FPGA_TDO B3 GND A4 FPGA_TCK B4 GND A5 +3.
H ARDWARE R EFERENCE G UIDE MICRO - LINE C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 36 6.5 Function of the micro-line ® Connector Pins 6.5.1 Connector A Pins A1 through A32: These signals are routed to the FPGA.
H ARDWARE R EFERENCE G UIDE MICRO - LINE C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 37 package or a custom FPGA design. Optionally, SDA0 can additionally be connected to the DSP's I 2 C interface #0, see chapter 7.
H ARDWARE R EFERENCE G UIDE MICRO - LINE C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 38 TXD : This pin is the transmit data output of the RS-232 interface. Output voltage is either -5.5 V (typical) or +5.5 V (typical).
H ARDWARE R EFERENCE G UIDE MICRO - LINE C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 39 DX1 / AXR0[5]: This pin has a dual function: If configured for McBSP usage, this pin is th e data transmit output of McBSP1.
H ARDWARE R EFERENCE G UIDE MICRO - LINE C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 40 CLKS1 / SCL1: This pin has a dual function: If configured for McBSP usage, this pin is the external input of the internal sample rate generator used for McBSP1.
H ARDWARE R EFERENCE G UIDE MICRO - LINE C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 41 DR0 / AXR0[0]: This pin has a dual function: If configured for McBSP usage, this pin is th e data receive input of McBSP0.
H ARDWARE R EFERENCE G UIDE MICRO - LINE C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 42 FSR0 / AFSR0: This pin has a dual function: If configured for McBSP usage, this pin is the receiver frame sync input or output of McBSP0.
H ARDWARE R EFERENCE G UIDE MICRO - LINE C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 43 Pins E30 and E31: These signals are routed to the FPGA. Usage of these signals requires either an ORSYS board support package or a custom FPGA design.
H ARDWARE R EFERENCE G UIDE MICRO - LINE C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 44 7 Environment 7.1 Minimum Connections This chapter shows how to set up the C6713CPU for use without a micro-line ® Power Supply carrier board.
H ARDWARE R EFERENCE G UIDE MICRO - LINE C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 45 C9 D st andard PC RS-232 co nnector Sub-D 9 p in so cket; f its d irect l.
H ARDWARE R EFERENCE G UIDE MICRO - LINE C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 46 7.2 Changing the Bo ard Configuration This chapter shows the different hardware board configurations. The factory defaults are listed below.
H ARDWARE R EFERENCE G UIDE MICRO - LINE C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 47 R1 R7 2 R7 3 R6 4 R6 6 Figure 11: Location of configuration elements (bottom side) 7.2.2 Configurin g DSP Clock Speed R81 controls the setting of the CPUSPEED bit in the PLD's HWCFG register.
H ARDWARE R EFERENCE G UIDE MICRO - LINE C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 48 7.2.6 Configurin g CLKS1 / SCL1 Termination By default, a 10k pull-down resistor (R65) is installed for CLKS1 operation.
H ARDWARE R EFERENCE G UIDE MICRO - LINE C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 49 7.4 Supply Voltage The C6713CPU must be supplied with a voltage of nominal +3.3 V. The integrated switching voltage regulators generate all necessary on-board voltages.
H ARDWARE R EFERENCE G UIDE MICRO - LINE C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 50 7.9 Dimensions of the Board Figure 12 shows the dimensions of the C6713CPU. When the C6713CPU is stacked with other modules, board spacing is 14mm.
H ARDWARE R EFERENCE G UIDE MICRO - LINE C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 51 2.5 4 5.71 1.2 7 5.7 1 15, 24 17.
H ARDWARE R EFERENCE G UIDE MICRO - LINE C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 52 7.10 Spare micro-line ® Connectors The C6713CPU uses square connectors with 0.1 inch (2.54 mm) spa cing. In cont rast to previous micro-line ® CPU boards, the C6713CPU does not allow stacking other boards on top of it.
H ARDWARE R EFERENCE G UIDE MICRO - LINE C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 53 8 List of abbreviations used in this document BSP b oard s upport p ackag.
H ARDWARE R EFERENCE G UIDE MICRO - LINE C6713CPU Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 54 9 Literature references Further information that is not covered in this u ser's guide can be found in the documents liste d below.
Un point important après l'achat de l'appareil (ou même avant l'achat) est de lire le manuel d'utilisation. Nous devons le faire pour quelques raisons simples:
Si vous n'avez pas encore acheté Kane Industries C6713CPU c'est un bon moment pour vous familiariser avec les données de base sur le produit. Consulter d'abord les pages initiales du manuel d'utilisation, que vous trouverez ci-dessus. Vous devriez y trouver les données techniques les plus importants du Kane Industries C6713CPU - de cette manière, vous pouvez vérifier si l'équipement répond à vos besoins. Explorant les pages suivantes du manuel d'utilisation Kane Industries C6713CPU, vous apprendrez toutes les caractéristiques du produit et des informations sur son fonctionnement. Les informations sur le Kane Industries C6713CPU va certainement vous aider à prendre une décision concernant l'achat.
Dans une situation où vous avez déjà le Kane Industries C6713CPU, mais vous avez pas encore lu le manuel d'utilisation, vous devez le faire pour les raisons décrites ci-dessus,. Vous saurez alors si vous avez correctement utilisé les fonctions disponibles, et si vous avez commis des erreurs qui peuvent réduire la durée de vie du Kane Industries C6713CPU.
Cependant, l'un des rôles les plus importants pour l'utilisateur joués par les manuels d'utilisateur est d'aider à résoudre les problèmes concernant le Kane Industries C6713CPU. Presque toujours, vous y trouverez Troubleshooting, soit les pannes et les défaillances les plus fréquentes de l'apparei Kane Industries C6713CPU ainsi que les instructions sur la façon de les résoudre. Même si vous ne parvenez pas à résoudre le problème, le manuel d‘utilisation va vous montrer le chemin d'une nouvelle procédure – le contact avec le centre de service à la clientèle ou le service le plus proche.
